The present disclosure relates to semiconductor devices having chip-on-chip structures.
With recent miniaturization of semiconductor fabrication techniques, the number of transistors used for large scale integration (LSI) has been increasing. In addition, as components, especially systems, constituting LSI have become more and more complicated in larger scales, the memory capacity required for so-called system LSI have been expected to increase. In terms of cost, one of the most important issues is highly efficient assembly in system LSI incorporating a large-scale memory circuit.
To connect LSI to a package, wire bonding or flip-chip bonding is generally employed. In these bonding techniques, a memory circuit needs to be incorporated into a chip of system LSI itself or mounted on a mother substrate or a circuit substrate on which an LSI chip is mounted. Incorporation of a memory circuit into a chip is affected by the memory capacity. Mounting a memory circuit on a substrate has problems including an increased area of the substrate itself and an increased cost for mounting.
A chip-on-chip (COC) structure is a solution for the foregoing problems. FIG. 16 illustrates a cross section of a typical COC structure as described in, for example, Japanese Unexamined Patent Publication No. 2010-141080. As illustrated in FIG. 16, a first chip 11 and a second chip 12 each having an element formation surface on which a plurality of pads are provided are electrically connected to each other via bumps 14, and bonded to each other by an underfill resin material 15.
The first chip 11 is bonded to a substrate 13 such as a wiring substrate with a surface of the first chip 11 opposite to the second chip 12 facing the substrate 13. The upper surface (i.e., the element formation surface) of the first chip 11 is provided with pads for wire bonding, and electrically connected to the substrate 13 by wires 16. The first chip 11, the second chip 12, and the wires 16 are covered with a molding resin 17 (only whose outer contour is shown).
The use of the above-described COC structure enables the multiple chips 11 and 12 to be mounted on the substrate 13, and thus, achieves efficient bonding of a plurality of chips in a small area, as compared to typical wire bonding or flip-chip bonding techniques.
Japanese Unexamined Patent Publications Nos. 2007-207805 and 2005-183934 show configurations in each which a second semiconductor chip, which is located above a first semiconductor chip, does not coincide with the first semiconductor chip in plan view.